1. Field
Exemplary embodiments of the present invention relate to a nonvolatile memory device and a method for fabricating the same, and more particularly, to a nonvolatile memory device having a 3D structure in which a plurality of memory cells are stacked vertically from a substrate, and a method for fabricating the same.
2. Description of the Related Art
A nonvolatile memory device is a memory device, which maintains data stored therein although power supply is cut off. Currently, various nonvolatile memory devices, for example, Flash memory and the like are widely used.
Recently, as the improvement in integration degree of nonvolatile memory devices having a 2D structure in which memory cells are formed as a single layer over a semiconductor substrate approaches the limit, a nonvolatile memory device having a 3D structure in which a plurality of memory cells are formed along a channel layer protruding vertically from a semiconductor substrate has been proposed. Specifically, the nonvolatile memory device having a 3D structure may include a structure for storing changes in a floating gate electrode formed of a conductor and a structure for storing charges in a charge trap layer formed of an insulator.
FIGS. 1A and 1B are cross-sectional views of a conventional nonvolatile memory device having a 3D structure.
Referring to FIGS. 1A and 1B, the 3D nonvolatile memory device which stores charges in a floating gate electrode may include a channel layer 70 formed through a plurality of interlayer dielectric layers 20 and a plurality of control gate electrodes 30 which are alternately stacked over a substrate 10, a tunnel insulation layer 60 surrounding the channel layer 70, a floating gate electrode 50 interposed between the interlayer dielectric layers 20 and the tunnel insulation layer 60, and a charge blocking layer 40 surrounding the floating gate electrode 50.
In the nonvolatile memory device of FIG. 1A, the floating gate electrodes 50 positioned in the uppermost and lowermost parts are dummy floating gate electrodes adjacent to only one control gate electrode 30, and thus difficult to control. Accordingly, an abnormal program operation may occur, and a channel current may be reduced during a read operation.
Meanwhile, when a control gate electrode 30 is disposed on the substrate 10 as illustrated in FIG. 1B, a dummy floating gate electrode is not formed in the lowermost part, but the control gate electrode 30 is directly connected to the substrate 10. Therefore, the control gate electrode 30 is shorted to a well pick-up area, and cannot be controlled independently of the well pick-up area. Therefore, there is a demand for the development of a structure capable of solving the above-described problems.